The present invention relates to a xcfx80/2 phase shifter. More particularly, the present invention relates to a xcfx80/2 phase shifter capable of eliminating the effects of variation of elements in a circuit and parasitic capacitance and stably maintaining the phase difference of xcfx80/2 between output signals.
Recent development of digital mobile communication systems including a mobile phone system shows rapid progress. In the digital mobile communication systems, a roll-off xcfx80/4 shift QPSK (Quadrature Phase Shift Keying) method is generally used in order to improve the frequency utilization efficiency.
Generation of a roll-off xcfx80/4 shift QPSK signal requires a high-accuracy quadrature modulator. The quadrature modulator is a device for multiplying an input in-phase carrier and an input quadrature carrier having a phase difference of 90xc2x0 (xcfx80/2) from the in-phase carrier by an in-phase-component and a quadrature component (both of which are a base band signal) of a complex envelope signal of a modulated wave, respectively, for output from a synthesizer. Accordingly, a xcfx80/2 phase shifter is required which divides an input carrier into two signals, i.e., in-phase (0xc2x0) and quadrature (90xc2x0=xcfx80/2) carrier signals.
Accuracy of the xcfx80/2 phase shifter in the quadrature modulator greatly affects modulation accuracy of the quadrature modulator. The reason for this is as follows: if the phase difference between two output signals of the xcfx80/2 phase shifter varies from xcfx80/2, that is, if quadrature phase error occurs, independency of the in-phase/quadrature signals after synthesis is degraded, causing degradation in modulation due to crosstalk between the in-phase/quadrature signals. In general, in the case of a QPSK signal, quadrature phase accuracy must be within xc2x13xc2x0 in order to suppress this degradation to 0.1 dB or less as converted into a carrier-to-noise ratio (C/N).
As such a xcfx80/2 phase shifter for use in the quadrature modulator, the structure using a resistive element and a capacitive element is disclosed in, e.g., xe2x80x9cLow Power Quadrature Modulator IC""s for Digital Mobile Communicationsxe2x80x9d (Yasushi YAMAO et al., IEICE Transactions, ""93/11, Vol. J76-C-I, No. 11, pp. 453-455) and xe2x80x9cOrthogonal Modulatorxe2x80x9d (Japanese Patent Laying-Open No. 6-252970).
Referring to FIG. 14, a conventional xcfx80/2 phase shifter 40 receives an input signal SIGIN and outputs signals SIGa, SIGb that are out of phase from each other by xcfx80/2.
The xcfx80/2 phase shifter 40 includes a capacitor 41 coupled between an input node Ni for receiving the input signal SIGIN and a node Nb for outputting one output signal SIGb, and a resistive element 42 coupled between the node Nb and a ground node 45. The xcfx80/2 phase shifter 40 further includes a resistive element 43 coupled between the input node Ni and a node Na for outputting the other output signal SIGa, and a capacitor 44 coupled between the node Na and the ground node 45.
The xcfx80/2 phase shifter 40 is designed so that the capacitors 41, 44 have the same capacitance value C and the resistive elements 42, 43 have the same resistance value R.
FIG. 15 shows vector representation of an ideal output state of the xcfx80/2 phase shifter 40. Referring to FIG. 15, when the phase state of the signals is represented on the X-Y plane, the positive direction of the X axis corresponds to the phase xcex8in (0xc2x0) of the input signal SIGIN as a reference.
The phase of the output signal SIGb is advanced by xcex8b from that of the input signal SIGIN (xcex8in) by the capacitor 41 and the resistive element 42. In contrast, the phase of the other output signal SIGa is retarded by xcex8a from that of the input signal SIGIN (xcex8in) by the resistive element 43 and the capacitor 44.
Ideally, by designing the resistance value R and the capacitance value C in FIG. 14 according to the frequency of the input signal SIGIN so that xcex8b=xc2x145xc2x0 (+xcfx80/4) and xcex8a=xe2x88x9245xc2x0 (xe2x88x92xcfx80/4), the phase difference between the output signals SIGb and SIGa, that is, (xcex8bxe2x88x92xcex8a), can be set to xcfx80/2.
In other words, phase accuracy of the conventional xcfx80/2 phase shifter 40 depends on accuracy of the resistance value of the resistive elements and the capacitance value of the capacitors.
However, when such a xcfx80/2 phase shifter is fabricated on LSI (Large Scale Integrated circuit), manufacturing variation in the resistance value and capacitance value of the resistive elements and capacitors formed on the integrated circuit becomes problematic. Moreover, when the xcfx80/2 phase shifter 40 having such a structure is used in, e.g., mobile phones using a high-frequency carrier of, e.g., 100 MHz level or higher, the effects of parasitic elements on these circuits also become problematic.
Referring to FIG. 16, in the conventional xcfx80/2 phase shifter 40, the capacitor 41 coupled between the node Ni and the node Nb has Rtb1 and Rtb2 corresponding to the electrode resistance of the capacitor. The capacitance value Cb of the capacitor itself is not necessarily equal to the! design value C due to manufacturing variation.
The resistive element 42 coupled between the node Nb and the ground node 45 has a resistance value Rb varying from the design value R depending on the manufacturing variation, and an increased carrier frequency would cause parasitic capacitance Cpb.
Similarly, the resistive element 43 coupled between the node Ni and the node Na actually has a resistance value Ra that is not equal to the design value R due to the manufacturing variation, and operation in a high frequency region would cause parasitic capacitance Cpa. Moreover, the capacitor 44 coupled between the node Na and the ground node 45 actually has a capacitance value Ca that is not necessarily equal to the design value C due to the manufacturing variation, and has resistances Rta1 and Rta2 corresponding to the electrode resistance thereof.
FIG. 17 shows vector representation of the output state of the xcfx80/2 phase shifter 40 affected by these problems.
Referring to FIG. 17, as the resistance value and capacitance value of the capacitors 41, 44 and the resistive elements 42, 43 vary from the respective design values due to the manufacturing variation and the effects of the parasitic elements during high-frequency operation, the respective phase differences xcex8bxe2x80x2, xcex8axe2x80x2 between the output signals SIGb, SIGa and the input signal SIGIN vary from the respective design values xc2x145xc2x0 (+xcfx80/4), xe2x88x9245xc2x0 (xe2x88x92xcfx80/4).
This hinders accurate setting of the phase difference between the output signals SIGb and SIGa of the xcfx80/2 phase shifter to xcfx80/2. when such a xcfx80/2 phase shifter is used in, e.g., a quadrature modulator, the phase difference between the output signals of the xcfx80/2 phase shifter varies from xcfx80/2, degrading independency of in-phase/quadrature signals after synthesis. This results in a degraded image suppression ratio upon demodulation, hindering desired modulation accuracy from being obtained by the quadrature modulator.
It is an object of the present invention to provide the structure of a xcfx80/2 phase shifter for accurately adjusting the phase difference between output signals to xcfx80/2.
According to the present invention, a xcfx80/2 phase shifter includes a phase shifter circuit and a phase difference correction circuit. The phase shifter circuit receives an input signal and an inverted input signal thereof and produces first and second intermediate signals having a same amplitude and being out of phase from each other. The phase shifter circuit further produces first and second inverted intermediate signals respectively corresponding to the first and second intermediate signals with their respective phases inverted. The phase difference correction circuit receives the first and second intermediate signals produced by the phase shifter circuit and the first and second inverted intermediate signals and outputs a set of signals that are out of phase from each other by xcfx80/2. The phase difference correction circuit includes an adder circuit for outputting a first output signal obtained by first addition of the first intermediate signal and the second intermediate signal, and a second output signal obtained by second addition of the first intermediate signal and the second inverted intermediate signal.
Preferably, the phase shifter circuit outputs as analog signals the first and second intermediate signals and the first and second inverted intermediate signals. The phase difference correction circuit further includes a first amplitude regulation circuit for making respective amplitudes of the first and second intermediate signals and the first and second inverted intermediate signals from the phase shifter circuit equal to each other. The adder circuit conducts the first and second additions based on the first and second intermediate signals and the first and second inverted intermediate signals which are transmitted through the first amplitude regulation circuit.
Preferably, the phase shifter circuit outputs as digital signals the first and second intermediate signals and the first and second inverted intermediate signals. The phase difference correction circuit further includes a low pass filter for passing therethrough the first and second intermediate signals and the first and second inverted intermediate signals which are digital signals. The adder circuit conducts the first and second additions based on the first and second intermediate signals and the first and second inverted intermediate signals which are transmitted through the low pass filter.
In such a xcfx80/2 phase shifter, when represented by vectors, the first output signal and the second output signal that are respectively produced by the first and second additions based on the first and second intermediate signals having the same amplitude and being out of phase from each other correspond to a pair of diagonal lines of a rhombus formed by vectors representing the first and second intermediate signals. Therefore, the phase difference between the first output signal and the second output signal can be accurately set to xcfx80/2.